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PRELIMINARY
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
ICS853S024
General Description
The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer and HiPerClockSTM a member of theHiPerClockSTM family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS853S024 is characterized to operate from either a 3.3V or a 2.5V power supply. Guaranteed output skew characteristics make the ICS853S024 ideal for those clock distribution applications demanding well defined performance and repeatability.
Features
* * * * * * * * * * *
Twenty four LVPECL outputs. One differential clock input pair Differential input clock (CLK, nCLK) can accept the following signaling levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Maximum output frequency: >1.5GHz Translates any single ended input signal to 3.3V/ 2.5V LVPECL levels with resistor bias on nCLK input Output skew: 25ps (typical) tR / tF: 180ps (typical) Additive phase jitter, RMS: 0.111ps (typical) @ 312.5MHz Full 3.3V or 2.5V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) packages.
ICS
.
Block Diagram
CLK Pulldown nCLK Pullup
24 24
Pin Assignment
nQ0:nQ23 VCC VEE Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 VEE VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 3 46 4 45 ICS853S024 5 44 64-Lead TQFP, EPad 6 43 10mm x 10mm x 1mm 7 42 8 41 package body 9 40 Y Package 10 39 Top View 11 38 12 37 13 36 35 14 1 2 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11 VCC VEE VCC Q6 VEE VEE
Q0:Q23
VCC VCC nQ23
Q20 nQ19 Q19 nQ18 Q18 VCC
Q23 nQ22 Q22
nQ21 Q21 nQ20
nCLK CLK nQ17 Q17 nQ16 Q16 nQ15 Q15 nQ14 Q14 nQ13 Q13 nQ12 Q12 VCC VCC
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
Table 1. Pin Descriptions
Number 1, 16, 18, 31, 33, 34, 50, 63, 64 2, 15, 17, 32, 49 3, 4 5, 6 7, 8 9, 10 11, 12 13, 14 19, 20 21, 22 23, 24 25, 26 27, 28 29, 30 35, 36 37, 38 39, 40 41, 42 43, 44 45, 46 47 48 Name VCC VEE Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 Q6, nQ6 Q7, nQ7 Q8, nQ8 Q9, nQ9 Q10, nQ10 Q11, nQ11 Q12, nQ12 Q13, nQ13 Q14, nQ14 Q15, nQ15 Q16, nQ16 Q17, nQ17 CLK nCLK Power Power Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Pulldown Pullup/ Pulldown Type Description Power supply pins. Negative supply pins. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Non-inverting differential clock input. Inverting differential clock input. VCC/2 default when left floating.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 50 50 Maximum Units pF k k
RPULLDOWN Input Pulldown Resistor
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PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA 32.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. LVPECL Power Supply DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, TA = 0C to 70C
Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 200 Maximum 3.465 Units V mA
NOTE 1: Output terminated with 50 to VCC / 2. See Parameter Measurement Information Section.
Table 3B. Differential DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, TA = 0C to 70C
Symbol IIH Parameter CLK Input High Current nCLK CLK IIL VPP VCMR Input Low Current nCLK Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 A V V -5 150 A A Test Conditions Minimum Typical Maximum 150 Units A
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
Table 3C. LVPECL DC Characteristics, VCC = 3.3V 5%, TA = 0C to 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
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Table 3D. LVPECL DC Characteristics, VCC = 2.5V 5%, TA = 0C to 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.4 Typical Maximum VCC - 0.9 VCC - 1.5 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, TA = 0C to 70C
Parameter fMAX tPD Symbol Output Frequency Propagation Delay; NOTE 1 156.25 MHz, Integration Range: 12kHz - 20MHz tjit() Additive Phase Jitter, RMS; NOTE 2 312.5 MHz, Integration Range: 12kHz - 20MHz 1GHz, Integration Range: 12kHz - 20MHz tsk(o) tsk(pp) tR / tF odc Output Skew; NOTE 3, 4 Part-to-Part Skew; NOTE 4, 5 Output Rise/Fall Time Output Duty Cycle 20% to 80% 600 0.149 0.111 0.44 25 TBD 180 50 Test Conditions Minimum Typical Maximum 1.9 Units GHz ps ps ps ps ps ps ps %
All parameters are measured at f 1GHz, unless otherwise noted. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured on Aeroflex PN9000. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Measured at the output differential cross points. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
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Parameter Measurement Information
2V 2V
VCC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx VEE
LVPECL
nQx VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
VCC
nQx Qx
nCLK
V
PP
Cross Points
V
CMR
nQy Qy
CLK
tsk(o)
VEE
Differential Input Level
Output Skew
Par t 1
nQx Qx nQy Qy
nCLK CLK
Par t 2
nQ0:nQ21 Q0:Q21
tsk(pp)
tPD
Part-to-Part Skew
Propagation Delay
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Parameter Measurement Information, continued
nQ0:nQ21 Q0:Q21
80% t PW
t
PERIOD
80% VSW I N G
Clock Outputs x 100%
20% tR tF
20%
odc =
t PW t PERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 1. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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Recommendations for Unused Input and Output Pins
Inputs: CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs: LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
2.5V 2.5V 2.5V VCC = 2.5V R1 250 50 + 50 - - R3 250 50 + VCC = 2.5V
50
2.5V LVPECL Driver
R1 50 R2 50
2.5V LVPECL Driver
R2 62.5 R4 62.5
R3 18
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V VCC = 2.5V
50 +
50 -
2.5V LVPECL Driver
R1 50 R2 50
Figure 4C. 2.5V LVPECL Driver Termination Example
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EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
SOLDER PIN EXPOSED HEAT SLUG
SOLDER
PIN
SOLDER
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S024. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS853S024 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 200mA = 693mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 24 * 30mW = 720mW
Total Power_MAX (3.465V, with all outputs switching) = 693W + 720mW = 1.413W 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 32.5C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 1.413 W * 32.5C/W = 115.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 5. Thermal Resistance JA for 64 Lead TQFP, EPad, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 32.5C/W 1 26.6C/W 2.5 25.1C/W
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PRELIMINARY
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V.
* * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 6. JA vs. Air Flow Table for a 64 Lead TQFP, E-Pad
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 32.5C/W 1 26.6C/W 2.5 25.1C/W
Transistor Count
The transistor count for ICS853S024 is: 8336
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Package Outline and Package Dimensions
Package Outline - Y Suffix for 64 Lead TQFP, E-Pad
-HD VERSION EXPOSED PAD DOWN
Table 7. Package Dimensions for 64 Lead TQFP, E-Pad
JEDEC Variation: ACD All Dimensions in Millimeters Minimum Nominal Maximum 64 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 12.00 Basic 10.00 Basic 7.50 Ref. 4.5 5.0 5.5 0.50 Basic 0.45 0.60 0.75 0 7 0.08
Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L ccc
Reference Document: JEDEC Publication 95, MS-026
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Ordering Information
Table 7. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 853S024AYLF ICS853S024AYLF Lead-Free, 64 Lead TQFP, E-Pad Tray 0C to +70C 853S024AYLFT ICS853S024AYLF Lead-Free, 64 Lead TQFP, E-Pad 500 Tape & Reel 0C to +70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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